It has been a rather routine day. That’s good–it means I get to work on my agenda! I’m working on setting up a possible IEEE student branch meeting for later this month, but I don’t have enough information to get specific yet. This afternoon in the EGR 204 Microprocessors and Digital Logic Lab the students worked on simulating a digital circuit that incorporates hierachy. We use Altera’s Quartus II software for that. Next week my EGR 204 students will start their first design project.
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